PLL Lock-In

How it works

A PLL chains three blocks into a loop:

1. Phase detector (PD) — produces an error from the phase difference. The classic sinusoidal detector outputs e = sin(θref − θvco), which pushes the loop to align the two phases rather than drive them to zero.
2. Loop filter — smooths the error. A bare gain gives a type-I loop; adding an integrator gives type-II.
3. VCO — a voltage-controlled oscillator whose frequency is ω = ω₀ + K·v.

Here the reference is a chirp, sweeping slowly across the VCO's free-running frequency so you can watch acquisition happen. Lock is reached when $\theta_{ref} - \theta_{vco}$ stops growing and the phase-error trace flattens onto zero.

Type-I vs type-II

The filter order changes the loop's character, not just its speed:

• Type-I (proportional only) locks quickly but leaves a static phase error — it needs a steady offset to hold the VCO at the right frequency.
• Type-II (PI filter) adds an integrator that accumulates the error until the steady-state phase error is driven to zero. This is the default for clock recovery, frequency synthesis, and demodulation, where residual phase offset is unacceptable.

The knobs

• Loop bandwidth K — the overall loop gain. Higher K means faster acquisition and tighter tracking, at the cost of more noise let through; lower K is slower but quieter.
• Filter order — choose 1st order (proportional, type-I, leaves a static phase error) or 2nd order (PI, type-II, drives the steady-state phase error to zero).

Changing either control re-arms the chirp so you can replay the whole acquisition transient.

Further reading

• Phase-locked loop (Wikipedia)
• Best, Phase-Locked Loops: Design, Simulation, and Applications
• Gardner, Phaselock Techniques